Method of manufacture of a PCRAM memory cell

ABSTRACT

The invention provides a method of forming a resistance variable memory element and the resulting element. The method includes forming an insulating layer having an opening therein; forming a metal containing layer recessed in the opening; forming a resistance variable material in the opening and over the metal containing layer; and processing the resistance variable material and metal containing layer to produce a resistance variable material containing a diffused metal within the opening.

FIELD OF THE INVENTION

[0001] The invention relates to the field of random access memory (RAM)devices formed using a resistance variable material, and in particularto an improved method of manufacturing a resistance variable memoryelement.

BACKGROUND OF THE INVENTION

[0002] A well known semiconductor memory component is a random accessmemory (RAM). RAM permits repeated read and write operations on memoryelements. Typically, RAM devices are volatile, in that stored data islost once the power source is disconnected or removed. Non-limitingexamples of RAM devices include dynamic random access memory (DRAM),synchronized dynamic random access memory (SDRAM) and static randomaccess memory (SRAM). In addition, DRAMS and SDRAMS also typically storedata in capacitors which require periodic refreshing to maintain thestored data.

[0003] Recently resistance variable memory elements, which includeprogrammable conductor memory elements, have been investigated forsuitability as semi-volatile and non-volatile random access memoryelements. Generally a programmable conductor memory element includes aninsulating dielectric material formed of a chalcogenide glass disposedbetween two electrodes. A conductive material, such as silver, isincorporated into the dielectric material. The resistance of thedielectric material can be changed between high resistance and lowresistance states. The programmable conductor memory is normally in ahigh resistance state when at rest. A write operation to a lowresistance state is performed by applying a voltage potential across thetwo electrodes.

[0004] When set in a low resistance state, the state of the memoryelement will remain intact for minutes or longer after the voltagepotentials are removed. Such material can be returned to its highresistance state by applying a reverse voltage potential between theelectrodes as used to write the element to the low resistance state.Again, the highly resistive state is maintained once the voltagepotential is removed. This way, such a device can function, for example,as a resistance variable memory element having two resistance states,which can define two logic states.

[0005] One preferred resistance variable material comprises achalcogenide glass, for example, a Ge_(x)Se_(100−x) glass. One method offorming a resistance variable memory element based on chalcogenide glassincludes forming a lower electrode over a substrate, forming aninsulating layer over the lower electrode, forming an opening in theinsulating layer to expose the lower electrode, forming a metalcontaining chalcogenide glass in the opening, recessing the metalcontaining chalcogenide glass, and forming an upper electrode overlyingthe insulating layer and the recessed metal containing chalcogenideglass. The resistance variable memory element can be recessed using adry etch or plasma etch. The chemistries used in the dry etch or plasmaetch produce inherent sidewalls of chemical compounds on the photoresist or structure used to define the etch which are very difficult toremove.

[0006] A specific example of a metal containing chalcogenide glass isgermanium-selenide (Ge_(x)Se_(100−x)) containing silver (Ag). A methodof providing silver to the germanium-selenide composition is toinitially form a germanium-selenide glass and then deposit a thin layerof silver upon the glass, for example by sputtering, physical vapordeposition, or other known technique in the art. The layer of silver maybe irradiated, preferably with electromagnetic energy at a wavelengthless than 600 nanometers, so that the energy passes through the silverand to the silver/glass interface, to break a chalcogenide bond of thechalcogenide material such that the glass is doped with silver. Silvermay also be provided to the glass by processing the glass with silver,as in the case of a silver-germanium-selenide glass. Another method forproviding metal to the glass is to provide a layer of silver-selenide ona germanium-selenide glass.

[0007] It would be desirable to have an improved method of fabricating aresistance variable memory element, which does not produce undesirableetch chemistry sidewalls.

BRIEF SUMMARY OF THE INVENTION

[0008] The present invention provides a method of fabricating aresistance variable memory element which inhibits production ofundesirable etch chemistry sidewalls. In a first embodiment, the methodincludes forming an insulating layer over a first electrode; forming anopening in the insulating layer to expose a portion of the firstelectrode; forming a metal material in the opening; depositing aresistance variable material over the metal material and in the opening;processing the resistance variable material to diffuse metal ions fromthe metal material into the resistance variable material to form a metalcontaining resistance variable material in the opening; and forming asecond electrode over the insulating layer and over the metal containingresistance variable material.

[0009] The metal material is preferably silver, the resistance variablematerial is preferably a germanium-selenium composition, and theresulting metal containing resistance variable material is preferably asilver-germanium-selenium composition.

[0010] In another embodiment a metal-chalcogenide layer, for example,silver selenide is formed over the metal material and a secondresistance variable material, for example a second germanium-seleniumcomposition, is formed over the metal-chalcogenide layer, prior to theformation of the second electrode.

[0011] These and other features and advantages of the invention will bemore apparent from the following detailed description, which is providedin connection with the accompanying drawings and illustrate exemplaryembodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0012]FIG. 1 is a cross-sectional view depicting a semiconductorsubstrate at an initial stage of processing towards a resistancevariable memory element.

[0013]FIG. 2 is a subsequent cross-sectional view taken from FIG. 1 at astage of processing subsequent to that shown in FIG. 1.

[0014]FIG. 3 is a subsequent cross-sectional view taken from FIG. 2 at astage of processing subsequent to that shown in FIG. 2.

[0015]FIG. 4 is a subsequent cross-sectional view taken from FIG. 3 at astage of processing subsequent to that shown in FIG. 3.

[0016]FIG. 5 is a subsequent cross-sectional view taken from FIG. 4 at astage of processing subsequent to that shown in FIG. 4.

[0017]FIG. 6 is a subsequent cross-sectional view taken from FIG. 5 at astage of processing subsequent to that shown in FIG. 5.

[0018]FIG. 7 is a subsequent cross-sectional view taken from FIG. 6 at astage of processing subsequent to that shown in FIG. 6.

[0019]FIG. 8 is a subsequent cross-sectional view taken from FIG. 7 at astage of processing subsequent to that shown in FIG. 7.

[0020]FIG. 9A is a subsequent cross-sectional view taken from FIG. 7 ata stage of processing subsequent to that shown in FIG. 7 in accordancewith a second embodiment of the invention.

[0021]FIG. 9B is a subsequent cross-sectional view taken from FIG. 9A ata stage of processing subsequent to that shown in FIG. 9A in accordancewith the second embodiment of the invention.

[0022]FIG. 9C is a subsequent cross-sectional view taken from FIG. 9B ata stage of processing subsequent to that shown in FIG. 9B in accordancewith the second embodiment of the invention.

[0023]FIG. 10 illustrates a process according to an embodiment of thepresent invention.

[0024]FIG. 11 illustrates an exemplary construction of a resistancevariable memory element in accordance with the second embodiment of theinvention.

[0025]FIG. 12 is a processor based system having one or more memorydevices that contains resistance variable memory elements according tothe present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0026] In the following detailed description, reference is made tovarious specific structural and process embodiments of the invention.These embodiments are described with sufficient detail to enable thoseskilled in the art to practice the invention. It is to be understoodthat other embodiments may be employed, and that various structural,logical and electrical changes may be made without departing from thespirit or scope of the invention.

[0027] The term “substrate” used in the following description mayinclude any supporting structure including, but not limited to, aplastic or a semiconductor substrate that has an exposed substratesurface. Semiconductor substrates should be understood to includesilicon, silicon-on-insulator (SOI), silicon-on-sapphire (SOS), dopedand undoped semiconductors, epitaxial layers of silicon supported by abase semiconductor foundation, and other semiconductor structures. Whenreference is made to a substrate or wafer in the following description,previous process steps may have been utilized to form regions orjunctions in or over the base semiconductor or foundation.

[0028] The term “silver” is intended to include not only elementalsilver, but silver with other trace metals or in various alloyedcombinations with other metals as known in the semiconductor industry,as long as such silver alloy is conductive, and as long as the physicaland electrical properties of the silver remain unchanged.

[0029] The term “silver-selenide” is intended to include various speciesof silver-selenide, including some species which have a slight excess ordeficit of silver, for instance, Ag₂Se, Ag_(2+x)Se, and Ag_(2−x)Se.

[0030] The term “semi-volatile memory device” is intended to include anymemory device which is capable of maintaining its memory state afterpower is removed from the device for a prolonged period of time. Thus,semi-volatile memory devices are capable of retaining stored data afterthe power source is disconnected or removed. The term “semi-volatilememory device” as used herein includes not only semi-volatile memorydevices, but also non-volatile memory devices.

[0031] The term “resistance variable memory element” is intended toinclude any memory element, including programmable conductor memoryelements, semi-volatile memory elements, and non-volatile memoryelements which exhibit a resistance change in response to an appliedvoltage.

[0032] The present invention relates to a process for forming aresistance variable memory element. The invention will now be explainedwith reference to FIGS. 1-10, which illustrate exemplary embodiments ofa resistance variable memory element 100 in accordance with theinvention. FIG. 10 shows an exemplary processing sequence for forming aresistance variable memory element in an exemplary embodiment of theinvention.

[0033] Referring to FIGS. 1 and 10, a semiconductor substrate 10, suchas a silicon wafer, is prepared for the processing steps of the presentinvention. A resistance variable memory element may be implemented invarious different technologies. One such application is in memorydevices. Insulating material 11, such as silicon dioxide, is formed oversubstrate 10 in process segment 108. Next and as shown at processsegment 110, a first electrode 12, is formed over the insulatingmaterial 11. The material used to form the electrode can be selectedfrom a variety of conductive materials, for example, tungsten, nickel,tantalum, titanium, titanium nitride, aluminum, platinum, or silver,among many others. Next and as shown at process segment 120, aninsulating layer 13, preferably formed of silicon nitride, is formedover the first electrode 12. This and any other subsequently formedinsulating layers may be formed of a conventional insulating nitride oroxide, among others. The present invention is not limited, however, tothe above-listed materials and other insulating and/or dielectricmaterials known in the industry may be used. The insulating layer may beformed by any known deposition methods, for example, by sputtering,chemical vapor deposition (CVD), plasma enhanced CVD (PECVD) or physicalvapor deposition (PVD), among others.

[0034] Referring now to FIG. 2 and processing segment 130 of FIG. 10,the insulating layer 13 is etched to form an opening 22, which exposesthe first electrode 12. This is done by patterning a masking material 21and etching to remove unmasked portions of the insulating layer 13, withthe etch stopping once it reaches the first electrode 12.

[0035] Referring now to FIG. 3 and processing segment 140, the maskingmaterial 21 of FIG. 2 is stripped and a metal containing layer 31, suchas silver is formed to substantially fill the opening 22 and contact thefirst electrode 12. Silver-selenide may also be used as the metalcontaining layer 31.

[0036] Referring now to FIG. 4 and processing segment 150 of FIG. 10,the metal containing layer 31 is then planarized down to expose thesurface of insulating layer 13, by using an abrasive planarizationetching technique, such as chemical mechanical planarization (CMP).Thus, the metal containing layer 31 is left only in the opening 22.

[0037] Referring now to FIG. 5 and processing segment 160 of FIG. 10, apartial etchback, preferably a wet etch, is performed to remove aportion of the metal containing layer from the opening 22. An exemplarywet etch would incorporate HNO₃ and H₂O. Regardless of the type of etchused, it is desirable that the metal containing layer 31 is recessedwithin the opening 22 approximately 50% or less of the depth of opening22 and preferably is recessed by about 40 to about 50% of the depth, theimportance of which will become apparent later in the description of theprocess. Wet etching is preferred to alleviate the problem of a sidewallforming from etch chemicals. Also, as wet etching is performed down anopening, the isotropic nature of wet etching is not a constraint and theetching is self-aligned to the opening.

[0038] Referring now to FIG. 6 and processing segments 170 and 180, afirst resistance variable material 41 is formed over the insulatinglayer 13 and recessed metal containing layer 31. The first resistancevariable material 41 is deposited in such a manner so as to contact therecessed metal containing layer 31. In an exemplary embodiment, thefirst resistance variable material 41 is a chalcogenide glass and ispreferably a germanium-selenide glass. The germanium-selenide glasscomposition is preferably one having a Ge_(x)Se_(100−x) stoichiometry offrom about Ge₂₀Se₈₀ to about Ge₃₃Se₆₇, and is more preferably aboutGe₂₅Se₇₅. The first resistance variable material 41 may be deposited byany known deposition methods, for example, by sputtering, chemical vapordeposition (CVD), plasma enhanced CVD (PECVD) or physical vapordeposition (PVD).

[0039] In accordance with processing segment 180 shown in FIG. 10, andas indicated by arrows in FIG. 6, the substrate 10 is either irradiatedwith light or thermally treated in combination with light irradiation tocause sufficient diffusion of metal ions from recessed metal containinglayer 31 into the first resistance variable material 41. For example,the first resistance variable material 41 may be irradiated for about 5to 30 minutes at between about 1 mW/cm² to about 10 mW/cm² with light atfrom about 200 nm to about 600 nm wavelength. Additionally, theirradiation may be used in combination with a thermal process using atemperature of from about 50° C. to about 300° C. (depending upon theglass stoichiometry) and preferably about 110° C. for about 5 to about15 minutes and preferably 10 minutes. The irradiation process issufficient to cause the desired diffusion of metal ions from metalcontaining layer 31 into layer 41; however, the thermal process byitself is not used, but is only used in combination with the irradiationprocess.

[0040] Because of the confinement of the metal containing layer 31,metal ions are only incorporated into the resistance variable materialwithin the opening 22. By recessing the metal containing layer 31 withinthe opening 22 by about 40% to about 50% in processing segment 160, asufficient amount of the metal containing layer 31 is available fordiffusion of metal ions into the resistance variable material 41.

[0041] Referring now to FIG. 7, processing the substrate with lightirradiation, results in a metal containing resistance variable material51 being formed in the opening 22. Any residual resistance variablematerial over layer 13 is removed by a dry etch process in processingsegment 190 shown in FIG. 10. By removing the residual resistancevariable material, further metal doping of the memory element will notoccur during subsequent processing and volume expansion stress isreduced. The dry etch process is preferably a chemistry containing a gaswhich is selective between the resistance variable material 41 and themetal containing resistance variable material 51. For example, anexemplary selective dry etch process would include CF₄ gas and/or SF₆gas which are selective between Ge₂₅Se₇₅ and Ag_(x)(Ge₂₅Se₇₅)_(1−x), If,by chance, metal is doped into the resistance variable material above orto the side of the opening 22, the dry etch will not remove it, however,the stress of confining the doped area of the element is relievedthrough the top of the element resulting in an element that is mushroomshaped at the top of the opening 22. However, the mushroom shape is nota detriment to electrical performance.

[0042] Referring now to FIG. 8 and processing segment 200, a secondconductive electrode 61 is formed over the insulating layer 13 and metalcontaining resistance variable material 51 to complete the formation ofthe resistance variable memory element. The second electrode ispreferably formed of tungsten, however any suitable conductive materialsmay be used to form the second electrode 61. The resulting structureforms a resistance variable memory element comprising a metal containingresistance variable material (i.e., such as a silver containingchalcogenide glass layer) and at least two conductive electrodes, namelyelectrodes 12 and 61. Conventional processing steps can then be carriedout to electrically couple the second electrode 61 to various circuitsof memory arrays.

[0043] FIGS. 1-8 depict a first exemplary embodiment of the invention.The structure depicted in FIG. 7 can also form the base of a secondembodiment of the invention. The second embodiment is now described withreference to FIGS. 9A-9C and process segments 300-320 of FIG. 10. Asshown in FIG. 9A and process segment 300 of FIG. 10 a metal containinglayer 71, such as silver-selenide, may be deposited over the metalcontaining resistance variable material 51. Any suitable metalcontaining layer 71 may be used. For instance, other suitable metalcontaining layers include silver-chalcogenide layers. Silver sulfide,silver oxide, and silver telluride are all suitable silver-chalcogenidesthat may be used in combination with any suitable metal containingresistance variable material 51. A variety of processes can be used toform the metal containing layer 71. For instance, physical vapordeposition techniques such as evaporative deposition and sputtering maybe used. Other processes such as chemical vapor deposition,co-evaporation or depositing a layer of selenium above a layer of silverto form silver-selenide can also be used.

[0044] Referring now to FIG. 9B and process segment 310, a secondresistance variable material 81, preferably a chalcogenide glass andmore preferably a germanium-selenide glass is deposited over the metalcontaining layer 71. The second germanium-selenide glass composition ispreferably one having a Ge_(x)Se_(100−x) stoichiometry between aboutGe₂₀Se₈₀ to about Ge₄₃Se₅₇ and is more preferably about Ge₄₀Se₆₀. Thesecond resistance variable material 41 may be deposited by any knowndeposition methods, for example, by sputtering, chemical vapordeposition (CVD), plasma enhanced CVD (PECVD) or physical vapordeposition (PVD).

[0045] Referring now to FIG. 9C and process segment 320 of FIG. 10, asecond conductive electrode 61 is formed over the second resistancevariable material 81 to complete the formation of a resistance variablememory element in accordance with the second embodiment of theinvention. The second electrode is preferably formed of tungsten,however any suitable conductive materials may be used to form the secondelectrode 61.

[0046] The resulting structure forms a resistance variable memoryelement comprising a metal containing resistance variable material 51(such as a silver-germanium-selenium glass layer), a metal containinglayer 71 (such as silver-selenide), a resistance variable material layer81 (such as a germanium-selenium glass layer), and at least twoconductive electrodes, namely electrodes 12 and 61. Conventionalprocessing steps can then be carried out to electrically couple thefirst and second electrode 12, 61 to various circuits of memory arrays.Providing a metal containing layer 71, such as silver-selenide, over themetal containing resistance variable material 51 and then providing asecond resistance variable material 81 over the metal containing layer71 allows the metal in the metal containing layer 71 to be more readilyavailable for switching.

[0047]FIG. 11 illustrates an exemplary construction of a resistancevariable memory element 100 employing the first embodiment of theinvention. A resistance variable memory element 100 in accordance withthe first embodiment of the invention is generally fabricated over asemiconductor substrate 10 and comprises a first insulating layer 11formed over a substrate 10. An access transistor 83 for accessing thememory element is illustrated as having source/drain regions 84, 85 anda gate stack 86. Access circuitry for operating a resistance variablememory cell may be fabricated in substrate 10. The insulating layer 11is provided over the circuitry, including transistor 83 and contains aconductive plug 161. In accordance with process segment 110, a firstmetal electrode 12 is formed within a second insulating layer 8 providedover the insulating layer 11 and plug 161. In accordance with processsegment 120, a third insulating layer 13 is formed over the firstelectrode 12 and second insulating layer 8. In accordance with processsegment 130, an etched opening is provided. A metal material and aresistance variable material are deposited in the opening and processedvia light irradiation in accordance with process segments 140-190 toform a metal containing resistance variable material 51 in the openingof the third insulating layer 13. As described, the metal containingresistance variable material 51 may be a silver-germanium-selenideglass.

[0048] In accordance with process segment 200 a second metal electrode54 is formed in contact with the silver-germanium-selenide glass 51.

[0049] The third insulating layer 13 may be formed, for example, betweenthe first electrode 12 and the second electrode 54 of any suitableinsulator, for example a nitride, an oxide, or other insulator. Thethird insulating layer 13 may be formed by any known deposition method,for example, by sputtering, chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD) or physical vapor deposition (PVD), among others. Apreferred insulating material is silicon nitride, but those skilled inthe art will appreciate that there are other numerous suitableinsulating materials for this purpose.

[0050] The first electrode 12 is electrically connected throughconductive plug 161 to a source/drain region 84 of access transistor 83.Source/drain region 85 is connected by another conductive plug 87 toother circuitry of a memory array. The gate of the transistor 83 may bepart of a word line which is connected to a plurality of resistancevariable memory elements 100 just as a bit line of a memory array may becoupled to a plurality of resistance variable memory elements throughplug 87.

[0051] The resistance variable memory element 100 of the invention maybe used in a random access memory device. FIG. 12 illustrates anexemplary processing system 900 which utilizes a resistance variablememory random access device 101 containing an array of resistancevariable memory elements 100 constructed as described above withreference to FIGS. 1-10. The processing system 900 includes one or moreprocessors 901 coupled to a local bus 904. A memory controller 902 and aprimary bus bridge 903 are also coupled the local bus 904. Theprocessing system 900 may include multiple memory controllers 902 and/ormultiple primary bus bridges 903. The memory controller 902 and theprimary bus bridge 903 may be integrated as a single device 906.

[0052] The memory controller 902 is also coupled to one or more memorybuses 907. Each memory bus accepts memory components 908, which includeat least one memory device 101 of the invention. Alternatively, in asimplified system, the memory controller 902 may be omitted and thememory components directly coupled to one or more processors 901. Thememory components 908 may be a memory card or a memory module. Thememory components 908 may include one or more additional devices 909.For example, the additional device 909 might be a configuration memory.The memory controller 902 may also be coupled to a cache memory 905. Thecache memory 905 may be the only cache memory in the processing system.Alternatively, other devices, for example, processors 901 may alsoinclude cache memories, which may form a cache hierarchy with cachememory 905. If the processing system 900 include peripherals orcontrollers which are bus masters or which support direct memory access(DMA), the memory controller 902 may implement a cache coherencyprotocol. If the memory controller 902 is coupled to a plurality ofmemory buses 907, each memory bus 907 may be operated in parallel, ordifferent address ranges may be mapped to different memory buses 907.

[0053] The primary bus bridge 903 is coupled to at least one peripheralbus 910. Various devices, such as peripherals or additional bus bridgesmay be coupled to the peripheral bus 910. These devices may include astorage controller 911, an miscellaneous I/O device 914, a secondary busbridge 915, a multimedia processor 918, and an legacy device interface920. The primary bus bridge 903 may also coupled to one or more specialpurpose high speed ports 922. In a personal computer, for example, thespecial purpose port might be the Accelerated Graphics Port (AGP), usedto couple a high performance video card to the processing system 900.

[0054] The storage controller 911 couples one or more storage devices913, via a storage bus 912, to the peripheral bus 910. For example, thestorage controller 911 may be a SCSI controller and storage devices 913may be SCSI discs. The I/O device 914 may be any sort of peripheral. Forexample, the I/O device 914 may be an local area network interface, suchas an Ethernet card. The secondary bus bridge may be used to interfaceadditional devices via another bus to the processing system. Forexample, the secondary bus bridge may be an universal serial port (USB)controller used to couple USB devices 917 via to the processing system900. The multimedia processor 918 may be a sound card, a video capturecard, or any other type of media interface, which may also be coupled toone additional devices such as speakers 919. The legacy device interface920 is used to couple legacy devices, for example, older styledkeyboards and mice, to the processing system 900.

[0055] The processing system 900 illustrated in FIG. 12 is only anexemplary processing system with which the invention may be used. WhileFIG. 12 illustrates a processing architecture especially suitable for ageneral purpose computer, such as a personal computer or a workstation,it should be recognized that well known modifications can be made toconfigure the processing system 900 to become more suitable for use in avariety of applications. For example, many electronic devices whichrequire processing may be implemented using a simpler architecture whichrelies on a CPU 901 coupled to memory components 908 and/or memoryelements 100. These electronic devices may include, but are not limitedto audio/video processors and recorders, gaming consoles, digitaltelevision sets, wired or wireless telephones, navigation devices(including system based on the global positioning system (GPS) and/orinertial navigation), and digital cameras and/or recorders. Themodifications may include, for example, elimination of unnecessarycomponents, addition of specialized devices or circuits, and/orintegration of a plurality of devices.

[0056] The above description and drawings are only to be consideredillustrative of exemplary embodiments, which achieve the features andadvantages of the present invention. Modification and substitutions tospecific process conditions and structures can be made without departingfrom the spirit and scope of the present invention. Accordingly, theinvention is not to be considered as being limited by the foregoingdescription and drawings, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A method of fabricating a resistance variablememory element, comprising the acts of: forming a first electrode;forming an insulating layer over said first electrode; forming anopening in said insulating layer to expose a portion said firstelectrode; forming a metal containing layer in said opening; forming aresistance variable material over said metal containing layer in saidopening; processing said resistance variable material and metalcontaining layer to diffuse metal from said metal containing layer intosaid resistance variable material to form a metal containing resistancevariable material in said opening; and forming a second electrode oversaid insulating layer and over said metal containing resistance variablematerial.
 2. The method of claim 1 wherein said act of forming saidmetal containing layer in said opening further comprises forming saidmetal containing layer over said insulating layer and planarizing saidformed metal containing layer to expose a surface of said insulatinglayer.
 3. The method of claim 2 further comprising the act of: removinga portion of said metal containing layer to recess said metal containinglayer in said opening prior to forming said resistance variable materialin said opening.
 4. The method of claim 3 wherein less than about 50% ofsaid metal containing layer is removed to recess said metal containinglayer within said opening.
 5. The method of claim 4 wherein about 40% toabout 50% of said metal containing layer is removed to recess said metalcontaining layer in said opening.
 6. The method of claim 1 wherein saidact of forming said resistance variable material over said metalcontaining layer and in said opening further comprises forming saidresistance variable material over said insulating layer.
 7. The methodof claim 6 further comprising the act of processing said element withlight irradiation to form said metal containing resistance variablematerial in said opening.
 8. The method of claim 7 further comprisingthe act of selectively etching any remaining resistance variablematerial after processing said element with light irradiation to formsaid metal containing resistance variable material in said opening. 9.The method of claim 8 wherein said selective etch comprises dry etching.10. The method of claim 9 wherein said dry etch uses a CF₄ gas.
 11. Themethod of claim 9 wherein said dry etch uses an SF₆ gas.
 12. The methodof claim 1 wherein said act of processing said resistance variablematerial and said metal containing layer comprises irradiation withlight.
 13. The method of claim 12 wherein said light irradiation isperformed for approximately 5 to about 30 minutes at from about 1 mW/cm²to about 10 mW/cm² with a light having a wavelength of from about 200 nmto about 600 nm.
 14. The method of claim 12 further comprising thermallyheating said element at a temperature of about 50° C. to about 300° C.for about 5 to about 15 minutes.
 15. The method of claim 14 comprisingthermally heating said element at about 110° C.
 16. The method of claim1 wherein said metal containing layer comprises a silver layer.
 17. Themethod of claim 1 wherein said metal containing layer comprises asilver-selenide layer.
 18. The method of claim 16 wherein saidresistance variable material comprises germanium-selenium.
 19. Themethod of claim 18 wherein said germanium-selenium has a stoichiometryof from Ge₂₀Se₈₀ to about Ge₃₃Se₆₇.
 20. The method of claim 18 whereinsaid germanium-selenium has a stoichiometry of about Ge₂Se₇₅.
 21. Themethod of claim 18 wherein said metal containing resistance variablematerial comprises silver-germanium-selenium.
 22. The method of claim 1further comprising forming a second metal containing layer over saidmetal containing resistance variable material.
 23. The method of claim22 wherein said second metal containing layer comprises asilver-selenide layer.
 24. The method of claim 22 further comprisingdepositing a second resistance variable material over said second metalcontaining layer.
 25. The method of claim 22 wherein said secondresistance variable material comprises germanium-selenium.
 26. Themethod of claim 25 wherein said germanium-selenium composition has astoichiometry of from about Ge₂₀Se₈₀ to about Ge₄₃Se₅₇.
 27. The methodof claim 26 wherein said germanium-selenium composition has astoichiometry of about Ge₄₀Se₆₀.
 28. A method of fabricating aresistance variable memory element, comprising the acts of: forming afirst electrode on a substrate: forming an insulating layer overlyingsaid first electrode; etching an opening in said insulating layer toexpose said first electrode; depositing a silver containing material insaid opening and overlying said insulating layer; planarizing saidsilver containing material to expose said insulating layer; recessingsaid silver containing material in said opening; depositing agermanium-selenium layer overlying said recessed silver containingmaterial and said insulating layer; processing said germanium-seleniumlayer and said silver containing material with light irradiation to forma silver-germanium-selenium material in said opening; removing anyresidual germanium-selenium layer overlying said insulating layer; andforming a second electrode overlying said insulating layer and saidsilver-germanium-selenium material formed in said opening.
 29. Themethod of claim 28 wherein said act of recessing said silver containingmaterial in said opening comprises a wet etch in the presence of HNO₃and H₂O.
 30. The method of claim 28 wherein said silver containingmaterial is recessed to less than 50% of the depth of said opening. 31.The method of claim 30 wherein said silver containing material isrecessed to between about 40% to about 50% of the depth of said opening.32. The method of claim 28 wherein said act of removing any residualgermanium-selenium layer comprises a dry etch in the presence of CF₄.33. The method of claim 28 wherein said act of removing any residualgermanium-selenium layer comprises a dry etch in the presence of SF₆.34. The method of claim 28 wherein said light irradiation is performedfor approximately 5 to about 30 minutes at from about 1 mW/cm² to about10 mW/cm² with a light having a wavelength of from about 200 nm to about600 nm.
 35. The method of claim 28 further comprising thermally heatingsaid element at a temperature from about 50° C. to about 300° C. forabout 5 to about 15 minutes.
 36. The method of claim 35 comprisingthermally heating said element at about 110° C.
 37. The method of claim28 wherein said silver containing material comprises silver-selenide.38. The method of claim 28 wherein said germanium-selenium layer has astoichiometry of from about Ge₂₀Se₈₀ to about Ge₃₃Se₆₇.
 39. The methodof claim 38 wherein said germanium-selenium layer has a stoichiometry offrom about Ge₂Se₇₅.
 40. A method of fabricating a resistance variablememory element, comprising the acts of: forming a first electrode on asubstrate: forming an insulating layer overlying said first electrode;etching an opening in said insulating layer to expose a portion of saidfirst electrode; depositing a silver containing material in said openingand overlying said insulating layer; planarizing said silver containingmaterial to expose said insulating layer; recessing said silvercontaining material in said opening; depositing a firstgermanium-selenium layer over said recessed silver containing materialin said opening and overlying said insulating layer; processing saidfirst germanium-selenium layer and said silver containing material withlight irradiation to form a silver-germanium-selenium material in saidopening; removing any residual portions of said first germanium-seleniumlayer outside an area of said opening; depositing a silver-selenidelayer overlying said insulating layer and said silver-germanium-seleniummaterial formed in said opening; forming a second germanium-seleniumlayer over said silver-selenide layer; and forming a second electrodeover said second germanium-selenium layer.
 41. The method of claim 40wherein said act of recessing said silver containing material in saidopening comprises a wet etch in the presence of HNO₃ and H₂O.
 42. Themethod of claim 40 wherein said silver containing material is recessedto less than 50% of the depth of said opening.
 43. The method of claim42 wherein said silver containing material is recessed to between about40% to about 50% of the depth of said opening.
 44. The method of claim40 wherein said act of removing residual portions of said firstgermanium-selenium layer comprises a dry etch in the presence of CF₄.45. The method of claim 40 wherein said act of removing residualportions of said first germanium-selenium layer comprises a dry etch inthe presence of SF₆.
 46. The method of claim 40 wherein said lightirradiation is performed for approximately 5 to about 30 minutes at fromabout 1 mW/cm² to about 10 mW/cm² with a light having a wavelength offrom about 200 nm to about 600 nm.
 47. The method of claim 40 furthercomprising thermally heating said element at a temperature from about50° C. to about 300° C. for about 5 to about 15 minutes.
 48. The methodof claim 47 comprising thermally heating said element at about 110° C.49. The method of claim 40 wherein said first germanium-selenium layerhas a stoichiometry of from about Ge₂₀Se₈₀ to about Ge₃₃Se₆₇.
 50. Themethod of claim 49 wherein said first germanium-selenium layer has astoichiometry of about Ge₂₅Se₇₅.
 51. The method of claim 40 wherein saidsecond germanium-selenium layer has a stoichiometry of from aboutGe₂₀Se₈₀ to about Ge₄₃Se₅₇.
 52. The method of claim 51 wherein saidsecond germanium-selenium layer has a stoichiometry of about Ge₄₀Se₆₀.53. A self-aligning process for forming a resistance variable memoryelement, comprising the acts of: forming an opening in an insulatinglayer to expose a surface of an underlying conductor; forming a metalcontaining layer recessed in said opening; forming a glass material onsaid metal containing layer within said opening and over said insulatinglayer; processing said glass material to diffuse metal from said metalcontaining layer into said glass material to form a metal doped glassmaterial within said opening; and forming a second conductor overlyingsaid metal doped glass material.
 54. The method of claim 53 wherein saidact of forming a metal containing layer in said opening furthercomprises forming said metal containing layer over said insulatinglayer.
 55. The method of claim 54 further comprising the act ofplanarizing said metal containing layer formed over said insulatinglayer to expose a surface of said insulating layer before recessing saidmetal containing layer.
 56. The method of claim 53 further comprisingthe act of removing any residual glass material formed over saidinsulating layer and outside an area of said opening.
 57. The method ofclaim 53 wherein said act of recessing said metal containing layercomprises removing less than about 50% of said metal containing layer insaid opening.
 58. The method of claim 57 wherein said act of recessingsaid metal containing layer comprises removing about 40% to about 50% ofsaid metal containing layer in said opening.
 59. The method of claim 53wherein said act of processing said glass material to diffuse said metalinto said glass material includes irradiating said glass material andmetal containing layer with light.
 60. The method of claim 59 whereinsaid irradiation is performed for approximately 5 to about 30 minutes atfrom about 1 mW/cm² to about 10 mW/cm² with a light having a wavelengthof from about 200 nm to about 600 nm.
 61. The method of claim 59 furthercomprising thermally heating said element at a temperature from about50° C. to about 300° C. for about 5 to about 15 minutes.
 62. The methodof claim 61 comprising thermally heating said element at about 110° C.63. The method of claim 56 wherein said act of removing any residualglass material comprises a selective dry etch.
 64. The method of claim63 wherein said dry etch is performed in the presence of a CF₄ gas. 65.The method of claim 63 wherein said dry etch is performed in thepresence of a SF₆ gas.
 66. The method of claim 53 wherein said metalcontaining layer comprises a silver layer.
 67. The method of claim 53wherein said metal containing layer comprises a silver-selenide layer.68. The method of claim 66 wherein said glass material comprises agermanium-selenium composition.
 69. The method of claim 68 wherein saidgermanium-selenium composition has a stoichiometry of from aboutGe₂₀Se₈₀ to about Ge₃₃Se₆₇.
 70. The method of claim 69 wherein saidgermanium-selenium composition has a stoichiometry of about Ge₂₅Se₇₅.71. The method of claim 68 wherein said metal doped glass materialcomprises a silver-germanium-selenium composition.
 72. The method ofclaim 71 wherein said silver-germanium-selenium composition has agermanium-selenium stoichiometry of about Ge₂₅Se₇₅.
 73. The method ofclaim 53 further comprising forming a metal-chalcogenide layer over saidmetal doped glass material.
 74. The method of claim 73 wherein saidmetal-chalcogenide layer comprises a silver-selenide layer.
 75. Themethod of claim 73 further comprising depositing a second glass materialover said metal-chalcogenide layer.
 76. The method of claim 75 whereinsaid second glass material comprises a second germanium-seleniumcomposition.
 77. The method of claim 76 wherein said secondgermanium-selenium composition has a stoichiometry of from aboutGe₂₀Se₈₀ to about Ge₄₃Se₅₇.
 78. The method of claim 77 wherein saidsecond germanium-selenium composition has a stoichiometry of aboutGe₄₀Se₆₀.
 79. A resistance variable memory element comprising: a firstelectrode; an insulating layer having an opening in communication withsaid first electrode; a light irradiated germanium-selenium glass havingdiffused silver ions formed within said opening and in electricalcommunication with said first electrode; and a second electrode formedover said light irradiated germanium-selenium glass having diffusedsilver ions formed within said opening in electrical communication withsaid glass.
 80. The element of claim 79 wherein said silvergermanium-selenium glass has a germanium-selenium stoichiometry of fromabout Ge₂₀Se₈₀ to about Ge₃₃Se₆₇.
 81. The element of claim 80 whereinsaid silver germanium-selenium glass has a germanium-seleniumstoichiometry of about Ge₂₅Se₇₅.
 82. A memory element comprising: afirst electrode; an insulating layer having an opening in electricalcommunication with said first electrode; a light irradiatedsilver-germanium-selenium glass formed at least within said opening; asilver-selenide layer formed over and in electrical communication withsaid silver-germanium-selenium glass; a resistance variable materialformed over and in electrical communication with said silver-selenidelayer; and a second electrode formed over said resistance variablematerial and in electrical communication with said resistance variablematerial.
 83. The element of claim 82 wherein saidsilver-germanium-selenium glass has a germanium-selenium stoichiometryof between about Ge₂₀Se₈₀ and about Ge₄₃Se₅₇.
 84. The element of claim83 wherein said silver-germanium-selenium glass has a germanium-seleniumstoichiometry of between about Ge₂₅Se₇₅.
 85. The element of claim 82wherein said resistance variable material comprises a germanium-seleniumcomposition.
 86. The element of claim 85 wherein said resistancevariable material has a germanium-selenium stoichiometry of aboutGe₂₀Se₈₀ to about Ge₄₃Se₅₇.
 87. The element of claim 86 wherein saidresistance variable material has a germanium-selenium stoichiometry ofabout Ge₄₀Se₆₀.
 88. A processor-based system, comprising: a processor;and a memory circuit connected to said processor, said memory circuitincluding a resistance variable memory element comprising: a firstelectrode; an insulating layer having an opening in communication withsaid first electrode; a light irradiated silver-germanium-selenium glassformed at least within said opening; and a second electrode formed oversaid insulating layer and said silver-germanium-selenium glass.
 89. Thesystem of claim 84 wherein said silver-germanium-selenium glass has agermanium-selenium stoichiometry of between about Ge₂₀Se₈₀ to aboutGe₃₃Se₆₇.
 90. The system of claim 89 wherein saidsilver-germanium-selenium glass has a germanium-selenium stoichiometryof about Ge₂₅Se₇₅.
 91. A processor-based system, comprising: aprocessor; and a memory circuit connected to said processor, said memorycircuit including a resistance variable memory element comprising: afirst electrode; an insulating layer having an opening in communicationwith said first electrode; a light irradiated silver-germanium-seleniumglass formed at least within said opening; a silver-selenide layerformed over and in electrical communication with saidsilver-germanium-selenium glass; a resistance variable material formedover and in electrical communication with said silver-selenide layer;and a second electrode formed over said resistance variable material andin electrical communication with said resistance variable material. 92.The element of claim 91 wherein said silver-germanium-selenium glass hasa germanium-selenium stoichiometry of about Ge₂₀Se₈₀ to about Ge₃₃Se₆₇.93. The element of claim 92 wherein said silver-germanium-selenium glasshas a germanium-selenium stoichiometry of about Ge₂₅Se₇₅.
 94. Theelement of claim 91 wherein said resistance variable material comprisesa germanium-selenium composition.
 95. The element of claim 94 whereinsaid resistance variable material has a germanium-selenium stoichiometryof about Ge₂₀Se₈₀ to about Ge₄₃Se₅₇.
 96. The element of claim 95 whereinsaid resistance variable material has a germanium-selenium stoichiometryof about Ge₄₀Se₆₀.
 97. A method of fabricating a resistance variablememory element, comprising the acts of: forming an insulating layerhaving an opening therein; forming a silver layer recessed in saidopening; forming a germanium-selenium layer in said opening andoverlying said silver layer; and processing said silver layer and saidgermanium-selenium layer to produce a germanium-selenium material havingdiffused silver therein.
 98. The method of claim 97 wherein said act offorming said silver layer in said opening further comprises forming saidsilver layer over said insulating layer and planarizing said silverlayer to expose a surface of said insulating layer.
 99. The method ofclaim 98 further comprising the act of: removing a portion of saidsilver layer to recess said silver layer in said opening.
 100. Themethod of claim 99 wherein less than 50% of said metal material isremoved to recess said silver layer in said opening.
 101. The method ofclaim 100 wherein about 40% to about 50% of said silver layer is removedto recess said silver layer in said opening.
 102. The method of claim 97wherein said act of forming said germanium-selenium layer overlying saidsilver layer and in said opening further comprises forming saidgermanium-selenium layer over to said insulating layer.
 103. The methodof claim 102 further comprising the act of selectively etching anyresidual germanium-selenium layer.
 104. The method of claim 103 whereinsaid selective etch comprises dry etching.
 105. The method of claim 104wherein said dry etching uses a CF₄ gas.
 106. The method of claim 104wherein said dry etching uses a SF₆ gas.
 107. The method of claim 97further comprising the act of processing said element with lightirradiation to form said germanium-selenium material having diffusedsilver formed therein.
 108. The method of claim 97 wherein saidgermanium-selenium layer has a stoichiometry of about Ge₂₀Se₈₀ to aboutGe₄₃Se₅₇.
 109. The method of claim 108 wherein said germanium-seleniumlayer has a stoichiometry of about Ge₂₅Se₇₅.